Intel Pathfinder for RISC

Intel Pathfinder for RISC-V—a pre-silicon development environment that supports IP selection via testing for compatibility and performance—is unifying its Starter and Professional Editions into a single version. Intel is expected to share more details about this unification at the RISC-V Summit in San Jose, California on 12-15 December 2022.

Intel Pathfinder for RISC-V, which aids system-on-chip (SoC) designers with early-stage software development using FPGA and simulator platforms, was initially made available in two versions. The Starter Edition, intended for the hobbyist, academia and research community, has been available as a free download. The Professional Edition, which came with broad ecosystem support, targeted organizations involved in commercial RISC-V based silicon and software.

Figure 1 Individual users will be able to download the new unified version with its enhanced features while commercial developers will use this version while seeking custom extensions for vendor-specific capabilities. Source: Intel

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At the RISC-V Summit, Intel will also demonstrate new features as well as FPGA boards, SoC reference designs, and developer tools operating within a unified IDE. That includes a new Cyclone 10 GX development board that will be available in Q1 2023. Intel Pathfinder for RISC-V enables software development using FPGA platforms for early SoC development and verification and an easy migration path from FPGA to ASIC via Intel Foundry Services.

Additionally, a variety of RISC-V cores and other IPs are likely to be instantiated on FPGA and simulator platforms. For instance, CEVA, a supplier of DSP cores, is making its CEVA-BX audio DSPs and audio front-end software stack available on Intel Pathfinder for RISC-V. Then there is System Level Solutions, which has announced support for Intel Pathfinder for RISC-V via its USB host and device controller IPs for the Cyclone 10 GX development board.

Figure 2 FPGA boards are becoming an important platform for validating the integration of peripheral IPs in SoCs based on RISC-V architecture. Source: Intel

Reference designs, another crucial recipe in SoC designs based on RISC-V processors, will be another prominent highlight of the Intel Pathfinder offerings showcased at the summit. Take, for instance, Tessolve, expecting its first RISC-V based SoC reference design to be ready in early 2023. It’s using Intel Pathfinder for RISC-V as the preferred development environment.

Intel Pathfinder, which provides a common environment for accessing RISC-V and peripheral IPs for its FPGA boards, aims to save chip designers’ time in assembling and testing different IP combinations in a single environment. Moreover, it offers robust software and industry-standard toolchains for developing and prototyping complex SoCs.

Intel Pathfinder for RISC-V will showcase a diverse range of engineering samples at the RISC-V Summit to accelerate the adoption of this open processor architecture. That’s good news for the rapidly evolving open and modular RISC-V architecture. RISC-V is an open standard instruction set architecture (ISA) that offers chip designers new freedoms to configure a custom processor with standard extensions, configuration options, and custom instructions.

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